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data sheet ics859s0424bgi revision a october 12, 2011 1 ?2011 integrated device technology, inc. 4:4 differential-to-lvpecl/lvds clock multiplexer ICS859S0424I general description the ICS859S0424I is a 4:4 differential-to-lvpecl/ lvds clock multiplexer which can operate up to 3ghz. the outputs for this device can either be programmed to give lvpecl or lvds levels. the ICS859S0424I has four selectable differential pclkx, npclkx clock inputs. the pclkx, npclkx input pairs can accept lvpecl, lvds or cml levels. the fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. features ? high speed 4:1 differential multiplexer with a 1:4 fanout buffer ? four programmable differential lvpecl or lvds output pairs ? four selectable differential pclkx, npclkx input pairs ? pclkx, npclkx pairs can accept the following differential input levels: lvpecl, lvds, cml ? maximum output frequency: 3ghz ? translates any single ended input signal to lvpecl levels with resistor bias on npclkx inputs ? part-to-part skew: 100ps (maximum) ? propagation delay: 555ps (typical) @ 3.3v ? additive phase jitter, rms: 0.22ps (typical) @ 3.3v ? full 3.3v or 2.5v supply modes ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package ICS859S0424I 24-lead tssop 4.4mm x 7.8mm x 0.925mm package body g package top view pin assignment block diagram 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk_sel0 clk_sel1 pclk0 npclk0 pclk1 npclk1 pclk2 npclk2 pclk3 npclk3 oea oeb v cc v ee nqa0 qa0 nqa1 qa1 qb0 nqb0 qb1 nqb1 v cc_tap sel_ out qa0 nqa0 pclk0 clk_sel1 clk_sel0 oea oeb npclk0 pclk1 npclk1 pclk2 npclk2 pclk3 npclk3 0 0 0 1 1 0 1 1 qa1 nqa1 qb0 nqb0 qb1 nqb1 pullup/pulldown pulldown pulldown pulldown pullup pullup sel_out pullup pullup/pulldown pulldown pullup/pulldown pulldown pullup/pulldown pulldown
ics859s0424bgi revision a october 12, 2011 2 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer table 2. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 3. pin characteristics number name type description 1, 2 clk_sel0, clk_sel1 input pulldown clock select inputs. see table 4a. lvcmos / lvttl interface levels. 3 pclk0 input pulldown non- inverting differential lvpecl clock input. 4 npclk0 input pullup/ pulldown inverting differential lvpecl clock input. v cc /2 default when left floating. 5 pclk1 input pulldown non-inverting differential clock input. 6 npclk1 input pullup/ pulldown inverting differential lvpecl clock input. v cc /2 default when left floating. 7 pclk2 input pulldown non-inverting differential clock input. 8 npclk2 input pullup/ pulldown inverting differential lvpecl clock input. v cc /2 default when left floating. 9 pclk3 input pulldown non-inverting differential clock input. 10 npclk3 input pullup/ pulldown inverting differential lvpecl clock input. v cc /2 default when left floating. 11 oea input pullup output enable pin for bank a outputs. see table 4b. lvcmos/lvttl interface levels. 12 oeb input pullup output enable pin for bank b outputs. see table 4b. lvcmos/lvttl interface levels. 13 sel_out input pullup output select pin. when low, selects lvds leve ls. when high, selects lvpecl levels. lvcmos/lvttl in terface levels. see table 1b. 14 v cc_tap power power supply pin. see table 1a. 15, 16 nqb1, qb1 output differ ential output pair. lvpecl or lvds interface levels. 17, 18 nqb0, qb0 output differ ential output pair. lvpecl or lvds interface levels. 19, 20 nqa1, qa1 output differ ential output pair. lvpecl or lvds interface levels. 21, 22 nqa0, qa0 output differ ential output pair. lvpecl or lvds interface levels. 23 v ee power negative supply pin. 24 v cc power power supply pin. symbol parameter test conditions minimum typical maximum units c in input capacitance 2pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r vcc/2 input pullup/pulldown resistor 50 k ?
ics859s0424bgi revision a october 12, 2011 3 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer function tables table 4a. clock input function table table 4c. sel_out function table table 4b. v cc_tap function table table 4d. output enable function table inputs outputs clk_sel1 clk_sel0 qx[0:1], nqx[0:1] 0 0 pclk0, npclk0 (default) 0 1 pclk1, npclk1 1 0 pclk2, npclk2 1 1 pclk3, npclk3 input outputs sel_out qx[0:1], nqx[0:1] 1 lvpecl (default) 0lvds outputs output level supply v cc_tap qx[0:1], nqx[0:1 ] lvpecl 2.5v v cc lvpecl 3.3v v cc lvds 2.5v v cc lvds 3.3v float inputs outputs oea, oeb qx[0:1], nqx[0:1] 0 low/high 1 normal operation (default)
ics859s0424bgi revision a october 12, 2011 4 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 5a. lvpecl power supply dc characteristics, v cc = v cc_tap = 3.3v 5%, t a = -40c to 85c table 5b. lvpecl power supply dc characteristics, v cc = v cc_tap = 2.5v 5%, t a = -40c to 85c table 5c. lvds power supply dc characteristics, v cc = 3.3v 5%, t a = -40c to 85c table 5d. lvds power supply dc characteristics, v cc = v cc_tap = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current outputs, i o (lvds) continuos current surge current 50ma 100ma 10ma 15ma package thermal impedance, ja 82.8 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v cc power supply voltage 3.135 3.3 3.465 v v cc_tap power supply voltage 3.135 3.3 3.465 v i ee power supply current 72 ma i cc_tap power supply current 5ma symbol parameter test conditions minimum typical maximum units v cc power supply voltage 2.375 2.5 2.625 v v cc_tap power supply voltage 2.375 2.5 2.625 v i ee power supply current 66 ma i cc_tap power supply current 5ma symbol parameter test conditio ns minimum typi cal maximum units v cc positive supply voltage 3.135 3.3 3.465 v i cc power supply current 140 ma i cc_tap power supply current 5ma symbol parameter test conditions minimum typical maximum units v cc positive supply voltage 2.375 2.5 2.625 v v cc_tap positive supply voltage 2.375 2.5 2.625 v i cc power supply current 130 ma i cc_tap power supply current 5ma
ics859s0424bgi revision a october 12, 2011 5 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer table 5e. lvcmos/lvttl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, t a = -40c to 85c table 5f. lvpecl dc characteristics, v cc = 3.3v 5%, t a = -40c to 85c note 1: common mode input voltage is defined as v ih . note 2: outputs terminated with 50 ? to v cc ? 2v. table 5g. lvpecl dc characteristics, v cc = 2.5v 5%, t a = -40c to 85c note 1: common mode input voltage is defined as v ih . note 2: outputs terminated with 50 ? to v cc ? 2v. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v cc = 3.465v 2.2 v cc + 0.3 v v cc = 2.625v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.465v -0.3 0.8 v v cc = 2.625v -0.3 0.7 v i ih input high current clk_sel0, clk_sel1 v cc = v in = 3.465v or 2.625v 150 a oea, oeb, sel_out v cc = v in = 3.465v or 2.625v 10 a i il input low current clk_sel0, clk_sel1 v cc = 3.465v or 2.625v, v in = 0v -10 a oea, oeb, sel_out v cc = 3.465v or 2.625v, v in = 0v -150 a symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk0, npclk0, pclk1, npclk1 v cc = v in = 3.465v 150 a i il input low current pclk0, pclk1 v cc = 3.465v, v in = 0v -10 a npclk0, npclk1 v cc = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input voltage; note 1 1.2 v cc v v oh output high voltage; note 2 v cc ? 1.4 v cc ? 0.9 v v ol output low voltage; note 2 v cc ? 2.0 v cc ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk0, npclk0, pclk1, npclk1 v cc = v in = 2.625v 150 a i il input low current pclk0, pclk1 v cc = 2.625v, v in = 0v -10 a npclk0, npclk1 v cc = 2.625v, v in = 0v -150 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input voltage; note 1 1.2 v cc v v oh output high voltage; note 2 v cc ? 1.4 v cc ? 0.9 v v ol output low voltage; note 2 v cc ? 2.0 v cc ? 1.5 v v swing peak-to-peak output voltage swing 0.4 1.0 v
ics859s0424bgi revision a october 12, 2011 6 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer table 5h. lvds dc characteristics, v cc = 3.3v 5%, t a = -40c to 85c table 5i. lvds dc characteristics, v cc = v cc_tap = 2.5v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v od differential output vo ltage sel_out = 0 247 454 mv ? v od v od magnitude change sel_out = 0 50 mv v os offset voltage sel_out = 0 1.10 1.40 v ? v os v os magnitude change sel_out = 0 50 mv symbol parameter test conditio ns minimum typical maximum units v od differential output volt age sel_out = 0 247 454 mv ? v od v od magnitude change sel_out = 0 50 mv v os offset voltage sel_out = 0 1.10 1.40 v ? v os v os magnitude change sel_out = 0 50 mv
ics859s0424bgi revision a october 12, 2011 7 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer ac electrical characteristics table 6a. lvpecl ac characteristics, v cc = v cc_tap = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters are measured at ?out 1.5ghz, unless otherwise noted. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: measured on agilent e5052a signal source analyzer. refer to additive phase jitter section. note 3: defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. note 4: these parameters are guaranteed by characterization. not tested in production. note 5: defined as skew between outputs on different devices o perating a the same supply voltage, same frequency, same temperat ure and with equal load conditions. using the same type of input on each device, the output is measured at the differential cross point s. note 6: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential cross points. table 6b. lvpecl ac characteristics, v cc = v cc_tap = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters are measured at ?out 1.5ghz, unless otherwise noted. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: measured on agilent e5052a signal source analyzer. refer to additive phase jitter section. note 3: defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. note 4: these parameters are guaranteed by characterization. not tested in production. note 5: defined as skew between outputs on different devices o perating a the same supply voltage, same frequency, same temperat ure and with equal load conditions. using the same type of input on each device, the output is measured at the differential cross point s. note 6: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential cross points. symbol parameter test conditio ns minimum typical maximum units f out output frequency 3ghz t pd propagation delay; note 1 400 800 ps t jit buffer additive phase jitter, rms; note 2 100mhz, integration range: 12khz ? 20mhz 0.22 0.28 ps t sk(b) bank skew; note 3, 4 25 ps t sk(pp) part-to-part skew; note 4, 5 100 ps t sk(o) output skew; note 4, 6 25 ps t r / t f output rise/fall time 20% to 80% 50 245 ps odc output duty cycle 46 54 % mux isolation mux isolation ?out < 1.2ghz 45 db symbol parameter test conditio ns minimum typical maximum units f out output frequency 3ghz t pd propagation delay; note 1 400 800 ps t jit buffer additive phase jitter, rms; note 2 100mhz, integration range: 12khz ? 20mhz 0.22 0.28 ps t sk(b) bank skew; note 3, 4 25 ps t sk(pp) part-to-part skew; note 4, 5 100 ps t sk(o) output skew; note 4, 6 25 ps t r / t f output rise/fall time 20% to 80% 50 235 ps odc output duty cycle 46 54 % mux isolation mux isolation ?out < 1.2ghz 45 db
ics859s0424bgi revision a october 12, 2011 8 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer table 6c. lvds ac characteristics, v cc = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters are measured at ?out 1.5ghz, unless otherwise noted. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: measured on agilent e5052a signal source analyzer. refer to additive phase jitter section. note 3: defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. note 4: these parameters are guaranteed by characterization. not tested in production. note 5: defined as skew between outputs on different devices o perating a the same supply voltage, same frequency, same temperat ure and with equal load conditions. using the same type of input on each device, the output is measured at the differential cross point s. note 6: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential cross points. table 6d. lvds ac characteristics, v cc = v cc_tap = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters are measured at ?out 1.5ghz, unless otherwise noted. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: measured on agilent e5052a signal source analyzer. refer to additive phase jitter section. note 3: defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. note 4: these parameters are guaranteed by characterization. not tested in production. note 5: defined as skew between outputs on different devices o perating a the same supply voltage, same frequency, same temperat ure and with equal load conditions. using the same type of input on each device, the output is measured at the differential cross point s. note 6: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential cross points. symbol parameter test conditio ns minimum typical maximum units f out output frequency 3ghz t pd propagation delay; note 1 400 800 ps t jit buffer additive phase jitter, rms; note 2 100mhz, integration range: 12khz ? 20mhz 0.26 0.30 ps t sk(b) bank skew; note 3, 4 25 ps t sk(pp) part-to-part skew; note 4, 5 100 ps t sk(o) output skew; note 4, 6 25 ps t r / t f output rise/fall time 20% to 80% 50 200 ps odc output duty cycle 46 54 % mux isolation mux isolation ?out < 1.2ghz 45 db symbol parameter test conditio ns minimum typical maximum units f out output frequency 3ghz t pd propagation delay; note 1 400 800 ps t jit buffer additive phase jitter, rms; note 2 100mhz, integration range: 12khz ? 20mhz 0.26 0.31 ps t sk(b) bank skew; note 3, 4 25 ps t sk(pp) part-to-part skew; note 4, 5 100 ps t sk(o) output skew; note 4, 6 25 ps t r / t f output rise/fall time 20% to 80% 50 200 ps odc output duty cycle 46 54 % mux isolation mux isolation ?out < 1.2ghz 45 db
ics859s0424bgi revision a october 12, 2011 9 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements have issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. measured using a rohde & schwarz sma100 as the input source. additive phase jitter @ 100mhz 12khz to 20mhz = 0.22ps (typical) ssb phase noise dbc/hz offset frequency (hz)
ics859s0424bgi revision a october 12, 2011 10 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer parameter measureme nt information 3.3v lvpecl output load ac test circuit 3.3v lvds output load ac test circuit differential input level 2.5v lvpecl output load ac test circuit 2.5v lvds output load ac test circuit bank skew scope qx nqx v ee 2v v cc_tap v cc, -1.3v0.165v scope qx nqx lvds 3.3v5% power supply +? float gnd float v cc_tap v cc, v cc v ee v cmr cross points v pp pclk[0:3] pclk[0:3] scope qx nqx v ee v cc, 2v v cc_tap -0.5v0.125v scope qx nqx 2.5v5% power supply +? float gnd v cc, v cc_tap qxx:nqxx qxx:nqxx qxy:nqxy qxy:qxy t sk(b) x = a or b
ics859s0424bgi revision a october 12, 2011 11 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer parameter measurement in formation, continued part-to-part skew output duty cycle/pulse width/period lvpecl output rise/fall time output skew propagation delay lvds output rise/fall time t sk(pp) part 1 part 2 qx qy nqx nqy nqa0, nqa1 nqb0, nqb1 qa0, qa1 qb0, qb1 t pw t period t pw t period odc = x 100% 20% 80% 80% 20% t r t f v swing nqa[0:1] nqb[0:1] qa[0:1] qb0[0:1] t sk(o) nqx qx nqy qy qa[0:1] qb0[0:1] npclk[0:3] pclk[0:3] t pd nqa[0:1] nqb[0:1] 20% 80% 80% 20% t r t f v od nqa[0:1] nqb[0:1] qa[0:1] qb0[0:1]
ics859s0424bgi revision a october 12, 2011 12 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer parameter measurement in formation, continued differential output voltage setup mux isolation offset voltage setup ? ? ? 100 out out lvds dc input v od / ? v od v dd amplitude (db) a0 spectrum of output signal q mux _isol = a0 ? a1 (fundamental) frequency ? mux selects static input mux selects active input clock signal a1 out out lvds dc input ? ? ? v os / ? v os v dd
ics859s0424bgi revision a october 12, 2011 13 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer applications information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
ics859s0424bgi revision a october 12, 2011 14 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer 3.3v lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds, cml and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. pclk/npclk inpu t driven by a cml driver figure 2c. pclk/npclk input driven by a 3.3v lvpecl driver figure 2e. pclk/npclk input driven by a 3.3v lvds driver figure 2b. pclk/npclk input driven by a built-in pullup cml driver figure 2d. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple pclk npclk lvpecl input cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 ? r2 50 ? r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? pclk npclk 3.3v 3.3v lvpecl lvpecl input 3.3v r1 100 ? lvds pclk npclk 3.3v lvpecl input zo = 50 ? zo = 50 ? pclk npclk 3.3v lvpecl input 3.3v zo = 50 ? zo = 50 ? r1 100 ? cml built-in pullup r3 84 r4 84 r1 125 r2 125 r5 100 - 200 r6 100 - 200 pclk npclk 3.3v lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v lvpecl input c1 c2
ics859s0424bgi revision a october 12, 2011 15 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer 2.5v lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds, cml and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 3a. pclk/npclk inpu t driven by a cml driver figure 3c. pclk/npclk input driven by a 2.5v lvpecl driver figure 3e. pclk/npclk input driven by a 2.5v lvds driver figure 3b. pclk/npclk input driven by a built-in pullup cml driver figure 3d. pclk/npclk input driven by a 2.5v lvpecl driver with ac couple pclk npclk lvpecl input cml 2.5v zo = 50 ? zo = 50 ? 2.5v 2.5v r1 50 ? r2 50 ? r3 250 ? r4 250 ? r1 62.5 ? r2 62.5 ? 2.5v zo = 50 ? zo = 50 ? pclk npclk 2.5v 2.5v lvpecl lvpecl input 2.5v r1 100 ? lvds pclk npclk 2.5v lvpecl input zo = 50 ? zo = 50 ? pclk npclk 2.5v lvpecl input 2.5v zo = 50 ? zo = 50 ? r1 100 ? cml built-in pullup r6 100 ? -180 ? 3.3v lvpecl driv er r7 100 ? -180 ? zo = 50 ? r2 100 ? c1 zo = 50 ? r3 100 ? c2 r4 100 ? r1 100 ? 2.5v 3.3v pclk npclk
ics859s0424bgi revision a october 12, 2011 16 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer recommendations for unused input and output pins inputs: pclk/npclk inputs for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but ca n be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both si des of the differential output pair should either be left floating or terminated. lv d s o u t p u t s all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. termination for 2.5v lvpecl outputs figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c. figure 4a. 2.5v lvpecl driver termination example figure 4c. 2.5v lvpecl driver termination example figure 4b. 2.5v lvpecl dr iver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 ? r3 250 ? r2 62.5 ? r4 62.5 ? + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 ? r2 50 ? + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 ? r2 50 ? r3 18 ? + ?
ics859s0424bgi revision a october 12, 2011 17 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 5a. 3.3v lvpecl output termination figure 5b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ics859s0424bgi revision a october 12, 2011 18 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 6a can be used with either type of output structure. figure 6b , which can also be used with both output types, is an op tional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds termination lv d s driver lv d s driver lv d s receiver lv d s receiver z t c z o z t z o z t z t 2 z t 2 figure 6a. standard termination figure 6b. optional termination
ics859s0424bgi revision a october 12, 2011 19 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer power considerations (3.3v lvpecl outputs) this section provides information on power dissipati on and junction temperature for the ICS859S0424I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS859S0424I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 72ma = 249.5mw power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 4 * 30mw = 120mw total power_ max (3.465v, with all outputs s witching) = 249.5mw + 120mw = 369.5mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 82.8c/w per table 7a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.370w * 82.8c/w = 115.6c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7a. thermal resistance ja for 24 lead tssop, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standar d test boards 82.8c/w 78.5 76.3
ics859s0424bgi revision a october 12, 2011 20 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l] * (v cc_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cc v cc - 2v q1 rl 50 ?
ics859s0424bgi revision a october 12, 2011 21 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer power considerations (3.3v lvds outputs) this section provides information on power dissipati on and junction temperature for the ICS859S0424I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS859S0424I is the sum of t he core power plus the power dissipated in the load(s). the fol lowing is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v dd_max * i cc_max = 3.465v * 120ma = 415.8mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 82.8c/w per table 7b below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.416w * 82.8c/w = 119.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7b. thermal resistance ja for 24 lead tssop, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standar d test boards 82.8c/w 78.5 76.3
ics859s0424bgi revision a october 12, 2011 22 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer reliability information table 8. ja vs. air flow table for a 24 lead tssop transistor count the transistor count for ICS859S0424I is: 585 package outline and package dimensions package outline - g suffix for 24 lead tssop table 9. package dimensions reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standar d test boards 82.8c/w 78.5 76.3 all dimensions in millimeters symbol minimum maximum n 24 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.90 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics859s0424bgi revision a october 12, 2011 23 ?2011 integrated device technology, inc. ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 859s0424bgilf ics59s0424bil ?lead-free? 24 lead tssop tube -40 c to 85 c 859s0424bgilft ics59s0424bil ?lead-free? 24 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, su ch as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS859S0424I data sheet 4:4 differential-to-lvpecl/lvds clock multiplexer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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